Semiconductor device having one of patterned SOI and SON...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S202000, C257S067000, C257S211000, C257S206000, C257S203000, C257S074000, C257S369000

Reexamination Certificate

active

06906384

ABSTRACT:
A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

REFERENCES:
patent: 5612552 (1997-03-01), Owens
patent: 6140163 (2000-10-01), Gardner et al.
patent: 7-106434 (1995-04-01), None
patent: 8-17694 (1996-01-01), None
patent: 8-316431 (1996-11-01), None
patent: 10-303385 (1998-11-01), None
patent: 11-238860 (1999-08-01), None
patent: 2000-91534 (2000-03-01), None
patent: 2000-243944 (2000-09-01), None
S. M. Sze, “Physics of Semiconductor Devices,” John Wiley & Sons, New York, (1981) p. 451.
Ghavam G. Shahidi, “SOI Technology for the GHz Era,” Proc. International Symposium on VLSI Technology, Systems, and Applications, (2001), pp. 11-14.
Ghavam G. Shahidi, Carl A. Anderson, Barbara A. Chappell, Terry I. Chappell, James H. Comfort, Bijan Davari, Robert H. Dennard, Robert L. Franch, Patricia A. McFarland, James S. Neely, Tak H. Ning, Michael R. Polcari, and James D. Warnock, IEEE.
Jean-Pierre Colinge, “Thin Film SOI Technology: The Solution to Many Submicron CMOS Problems,” Technical Digest-Proc. IEDM, (1989) pp. 34.1.1-34.1.4.
U.S. Appl. No. 10/096,655, filed Mar. 14, 2002, Yamada et al.
U.S. Appl. No. 10/653,093, filed Sep. 3, 2003, Yamada et al.
U.S. Appl. No. 10/654,030, filed Sep. 4, 2003, Minami et al.
U.S. Appl. No. 09/650,748, filed Aug. 30, 2000, Unknown.
U.S. Appl. No. 09/995,594, filed Nov. 29, 2001, Pending.
U.S. Appl. No. 10/075,465, filed Feb. 15, 2002, Pending.
U.S. Appl. No. 10/078,344, filed Feb. 21, 2002, Pending.
U.S. Appl. No. 10/096,655, filed Mar. 14, 2002, Yamada et al.
U.S. Appl. No. 10/699,676, filed Nov. 4, 2003, Yamada et al.
Robert Hannon, et al., “0.25 μm Merged Bulk DRAM and SOI Logic Using Patterned SOI”, 2000 Symposium on VLSI Technology Digest of Technical Papers; Jun. 13, 2000 Ch. 7.4, pp. 66-67.
H. L. Ho, et al. “A 0.13 μm High-Performance SOI Logic Technology With Embedded DRAM for System-On-A-Chip Application”, 2001 IEDM Technical Digest, Dec. 2, 2001, pp. 503-506.

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