SRAM formation using shadow implantation

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell

Reexamination Certificate

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C257S401000

Reexamination Certificate

active

06924561

ABSTRACT:
A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

REFERENCES:
patent: 4996574 (1991-02-01), Shirasaki
patent: 2003/0102518 (2003-06-01), Fried et al.
Digh Hisamoto et al., “FinFet-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFet Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFet,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFet: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFet for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. Appl. No. 10/638,334, filed Aug. 12, 2003, entitled: “Systems and Methods for Forming Dense N-Channel and P-Channel Fins Using Shadow Implantation,” 16 page specification, 18 sheets of drawings.
Co-pending U.S. Appl. No. 10/429,697, filed May 6, 2003, entitled: “FinFet-Based SRAM Cell,” 16 page specification, 12 sheets of drawings.

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