Digital phase locked loop

Details Digital phase locked loop Digital phase locked loop

1995-05-15

1997-02-11

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 327156, 327159, H03D 324

Patent

active

056028849

ABSTRACT:
A digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop included a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in the output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.

REFERENCES:
patent: 4489342 (1984-12-01), Gollinger et al.
patent: 4520408 (1985-05-01), Velasquez
patent: 4577163 (1986-03-01), Culp
patent: 4611230 (1986-09-01), Nienaber
patent: 5187722 (1993-02-01), Petty
patent: 5349331 (1994-09-01), Mentzer
Proceedings of the 40th Annual Frequency Symposium 1986 IEEE New York, pp. 355-365 V. Reinhardt et al "A Short Survey of Frequency Synthesizer Techniques" see page 360 section entitle Direct Digital Synthesis see pp. 361, 362, entitled Phase Interpolation DDS see figures 7, 8, 13, 14.

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