Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-11-15
2005-11-15
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S711000
Reexamination Certificate
active
06966012
ABSTRACT:
A column redundancy circuitry and a method for implementing the same are provided. One exemplary method provides routing for an access request addressed to a defective cell. The method includes providing a redundant column within a memory circuit, the redundant column in communication with a sense amplifier. Next, a defective cell of a memory circuit is located and the address is programmed. An access request is then processed, the access request containing the address of the defective cell Finally, the access request is routed to the redundant column through enable circuitry. Some notable advantages include the conservation of surface area of the memory circuit induced by locating the redundant column within the memory circuit. The externalization of the fuse box, Built In Self Repair region and the logic circuitry from the memory core also provide increased flexibility.
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Aitken, R. et al.; Redundancy, repair, and test features of a 90nm embedded SRAM generator; Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on, Vol., Iss., Nov. 3-5, 2003; pp.: 467-474.
Artisan Components Inc.
Dildine R. Stephen
Martine & Penilla & Gencarella LLP
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