Methods and apparatus for packaging semiconductor devices

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C438S111000, C438S123000, C438S124000

Reexamination Certificate

active

06955941

ABSTRACT:
A method and apparatus for increasing the integrated circuit density of a thin small outline package (“TSOP”) semicondctor assembly is provided by stacking two semiconductor dice and electrically connecting the substantially centrally located bond pads of substantially identically arranged bond pads of each die to the same surface of a single lead frame. Each semiconductor die may be electrically connected to a plated, common connection surface of the lead frame. The lead frame may include downsets to properly position the semiconductor assembly within the package. Further, if bond wires are used as electrical connection elements, stitch bonding may be employed to enhance rigidity of the bond wires and to modify electrical characteristics of the electrical connection elements.

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patent: 2001/0014488 (2001-08-01), Akram
patent: 2002/0017722 (2002-02-01), Masuda
patent: 2003/0127423 (2003-07-01), Dlugokecki et al.

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