Static random access memory system with compensating-circuit...

Details Static random access memory system with compensating-circuit... Static random access memory system with compensating-circuit...

2005-11-22

2005-11-22

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

C365S203000, C365S189110

Reexamination Certificate

active

06967875

ABSTRACT:
The memory system includes a plurality of memory cells that are arranged for forming a column, and the plurality of memory cells are coupled with a first bitline and a second bitline individually. Additionally, the memory system further includes a bitline conditioning circuit to perform the pre-charge procedure thereof; and that includes a plurality of wordlines. Furthermore, the memory system further includes a compensating-circuit to keep the voltage that is requirement for the access procedure, wherein the bitline conditioning circuit and the compensating-circuit couple to receive a pair of complemental signals so as to control the interaction between the pre-charge procedure and the compensation procedure from each other.

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K. Noda et al. “A 1.9-μm2Loadless CMOS Four-Transistor SRAM Cell in a 0.18μm Logic Technology” 1998 IEEE, IEDM 98 pgs. 643-646, 22.8.1-22.8.4.

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