Integrated circuit FIFO memory devices that are divisible...

Details Integrated circuit FIFO memory devices that are divisible... Integrated circuit FIFO memory devices that are divisible...

2005-06-14

2005-06-14

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S031000, C710S033000, C710S051000, C710S053000, C710S057000, C711S101000, C711S154000, C711S156000, C711S170000

Reexamination Certificate

active

06907479

ABSTRACT:
Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially. The register file may include multiple register subfiles, and the controller may include multiple controller subblocks.

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U.S. Appl. No. 09/721,478, filed Nov. 22, 2000, Au et al.

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