Efficient microcode entry access from sequentially addressed...

Details Efficient microcode entry access from sequentially addressed... Efficient microcode entry access from sequentially addressed...

2005-10-18

2005-10-18

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to generate an address of a microroutine

C711S215000, C712S243000, C712S245000

Reexamination Certificate

active

06957322

ABSTRACT:
A microcode instruction unit for a processor may include a microcode memory having entries for storing microcode instructions. A decoder for the microcode memory may decode microcode addresses to select entries of the microcode memory. A microcode entry point generator may receive complex instructions and provide a microcode entry point address to the decoder for each complex instruction. Each microcode entry point address may have a bit-width greater than needed to encode all the entries of the microcode memory. The microcode memory decoder may decode each microcode entry point address to select an entry in the microcode memory storing the beginning of a microcode routine to implement the corresponding complex instruction. The decoder may sparsely decode the microcode address range so that not all entries of said microcode memory are sequentially addressed.

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“Pentium Processor User's Manual, vol. 3: Architecture and Programming Manual,” Intel Corporation, 1993, pp. 25-1 though 25-5.

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