Method for modeling semiconductor device and network

Details Method for modeling semiconductor device and network Method for modeling semiconductor device and network

2005-12-27

2005-12-27

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C703S014000, C257S351000

Reexamination Certificate

active

06981236

ABSTRACT:
A method for modeling a device and a network to be analyzed in a complex simulation. The modeling method includes a device extraction step for extracting the structure of each of a plurality of devices included in the network to create device models showing the individual extracted structures, a device connection step for connecting the respective device models through the intermediary of an insulating portion for cutting off the electrical connection between the respective device models, and a circuit connection step for connecting a network model showing the network portion, from which the plurality of devices extracted in the device extraction step have been excluded, to a predetermined device model among the connected device models.

REFERENCES:
patent: 5825673 (1998-10-01), Watanabe
patent: 6649980 (2003-11-01), Noguchi
patent: 09-082938 (1997-03-01), None
patent: 2000-260973 (2000-09-01), None

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