Integrated circuit and method of controlling same

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S305000, C713S501000

Reexamination Certificate

active

06959357

ABSTRACT:
Bus-connected circuits are made to operate stably and at high speed. A cache memory for high-speed access and a DRAM for low-speed access are connected to a CPU by an address bus, control bus and data transfer bus. A switch is provided in the bus at a point between the cache memory and DRAM and the switch is opened at the time of high-speed access. Since bus length is essentially shortened at such time, the cache memory can be accessed stably at high speed. When the DRAM is accessed, the switch is closed.

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