Encoding method having improved interleaving

Details Encoding method having improved interleaving Encoding method having improved interleaving

2005-11-01

2005-11-01

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S786000

Reexamination Certificate

active

06961889

ABSTRACT:
A method of encoding at least one input bit set of ordered bits with permutation position integers comprising encoding the input bit set using a first encoder having a multi-state register to provide a first output; selectively reordering the input bit set using an interleaver to provide a reordered input bit set; and encoding the reordered input bit set using a second encoder having a multi-state register to provide a second output; whereby the value of said second encoder register is the same as the value of said first encoder register upon completion of the procedure.

REFERENCES:
patent: 5703902 (1997-12-01), Ziv et al.
patent: 6772391 (2004-08-01), Shin
patent: 2002/0083395 (2002-06-01), Eroz et al.
W.J. Blackert, E.K. Hall, S.G. Wilson: “Turbo Code Termination And Interleaver Conditions”, Electronics Letters, vol. 31, No. 24, Nov. 23, 1995, pp. 2082-2084.
Divsalar D. et al.: “Turbo Codes For PCS Applications”, Proceedings of the International Conference on Communications (ICC), US, New York, IEEE, 1995 pp. 54-59.
Barbulescu A.S. et al.: “Terminating The Trellis Of Turbo-Codes In The Same State”, Electronics Letters, GB, IEE Stevenage, vol. 31, No. 1, Jan. 5, 1995, pp. 22-23-23.

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