Capacitor with a geometrical layout

Details Capacitor with a geometrical layout Capacitor with a geometrical layout

2005-12-13

2005-12-13

Wilson, Christian D. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S298000, C257S301000, C257S304000, C257S306000, C257S307000, C257S309000

Reexamination Certificate

active

06974994

ABSTRACT:
A capacitor includes an array of first conductive units and an array of second conductive units. Each of the first conductive units includes a hollow first conductive post that has lateral sides. The first conductive posts of the first conductive units are interconnected to form a grid that defines a plurality of lattices. Each of the second conductive units includes a second conductive post that is disposed in a respective one of the lattices and that has lateral sides that are surrounded by the lateral sides of the first conductive post of a respective one of the first conductive units. The first conductive post of each of the first conductive units and the second conductive post of the respective one of the second conductive units cooperatively define a charge space. A dielectric material fills the charge space.

REFERENCES:
patent: 5340763 (1994-08-01), Dennison
patent: 6215187 (2001-04-01), Ooto et al.
patent: 6410955 (2002-06-01), Baker et al.
patent: 6576946 (2003-06-01), Kanai et al.
patent: 6888217 (2005-05-01), Gilgen et al.

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