Static information storage and retrieval – Systems using particular element – Semiconductive
Patent
1995-07-18
1998-01-27
Fears, Terrell W.
Static information storage and retrieval
Systems using particular element
Semiconductive
365185, 257191, 257192, 257194, G11C 1300
Patent
active
057128146
ABSTRACT:
A nonvolatile memory having a cell comprising an N.sup.+ type source region and drain region embedded in a P.sup.- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.
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Chen, M.L., et al., "Constraints in P-Channel Device Engineering for Submicron CMOS Technologies," IEDM Tech. Dig., 1988, pp. 390-393.
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Buti et al., "A New Asymmetrical Halo Source GOLD Drain (HS-GOLD) Deep Sub-Half-Micrometer n-MOSFET Design for Reliability and Performance," in Proccedings of IEEE Transactions on Electron Devices 38(8):1757-1764, Aug. 1991.
Yoshikawa et al., "A Reliable Profiled Lightly-Doped Drain (PLD) Cell for High Density Submicron EPROMS and Flash EEPROMS," in Extended Abstracts of the 20th Conference on Solid State Devices and Materials, Tokyo, Japan, Aug. 24-26, 1988, pp. 165-168.
Hori, Takashi, "A New Submicron p-Channel MOSFET with LATIPS (Large-Tilt-Angle Implanted Punchthrough Stopper)",Journal of Electronic Engineering 26(267):128-131, Mar. 1989.
Ohshima et al., "Process and Device Technologies for 16Mbit EPROMs With Large-Tilt-Angle Implanted P-Pocket Cell," in Proceedings of the International Meeting of the Electron Devices Society, San Francisco, CA, Dec. 9-12, 1990, pp. 5.2.1-5.2.4.
Fratin Lorenzo
Ravazzi Leonardo
Riva Carlo
Carlson David V.
Fears Terrell W.
Santarelli Bryan A.
SGS--Thomson Microelectronics S.r.l.
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