Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2005-10-18
2005-10-18
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S613000, C438S123000
Reexamination Certificate
active
06955942
ABSTRACT:
In a step of covering a rear face resist, by recognizing position of a positioning mark exposed at a rear face of a conductive foil, position recognition of a conductive pattern of the rear face of every block or every conductive foil is performed indirectly, and a resist layer is formed except an opening portion forming the scheduled rear face electrode on the conductive pattern. Therefore, a method of manufacturing a circuit device shortened in time.
REFERENCES:
patent: 2001/0045625 (2001-11-01), Sakamoto et al.
patent: 9092769 (1997-04-01), None
patent: 2002009443 (2000-06-01), None
patent: 2002-76238 (2002-03-01), None
Kobayashi Yoshiyuki
Sakamoto Noriaki
Takahashi Kouji
Fish & Richardson PC
Huynh Yennhu B.
Jr. Carl Whitehead
Sanyo Electric Co,. Ltd.
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