Nonplanar device with stress incorporation layer and method...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S401000

Reexamination Certificate

active

06909151

ABSTRACT:
A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

REFERENCES:
patent: 5346839 (1994-09-01), Sundaresan
patent: 5563077 (1996-10-01), Ha
patent: 5578513 (1996-11-01), Maegawa
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6483156 (2002-11-01), Adkission et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6680240 (2004-01-01), Maszara
patent: 2002/0081794 (2002-06-01), Ito
patent: 2002/0167007 (2002-11-01), Yamazaki et al.
patent: 0 623 963 (1994-11-01), None
patent: WO 02/43151 (2002-05-01), None
International Search Report PCT/US03/26242.
International Search Report PCT/US 03/40320.
V. Subramanian et al., “A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100m MOSFETS” Proceeding of the 57th Annual Device Research Conference, pp. 28-29 (1999).
Hisamoto et al., “A Folded-channel MOSFET for Deepsub-tenth Micron Era”, 1998 IEEE International Electron Device Meeting Technical Digest, pp 1032-1034 (1998).
Huang et al., “Sub 50-nm FinFET: PMOS”, 1999 IEEE International Electron Device Meeting Technical Digest, pp 67-70 (1999).
Auth et al., “Vertical, Fully-Depleted, Surroundings Gate MOSFETS On sub-0.1 um Thick Silicon Pillars”, 1996 54th Annual Device Research Conference Digest, pp 108-109 (1996).
Hisamoto et al., “A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET”, IEEE Electron Device Letters, V. 11(1), pp36-38 (1990).
Jong-Tae Park et al., “Pi-Gate SOI MOSFET” IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, pp. 405-406.
Hisamoto, Digh et al. “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm”, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
International Search Report PCT/US 03/39727.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Nonplanar device with stress incorporation layer and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonplanar device with stress incorporation layer and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonplanar device with stress incorporation layer and method... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3471583

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.