Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2005-02-22
2005-02-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S683000
Reexamination Certificate
active
06858524
ABSTRACT:
A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The method enables the use of hydrogen plasma, high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in the processing steps subsequent to the deposition of the gate dielectric layer of the device. The ALD process for forming the barrier layer is performed essentially in the absence of plasma and reactive hydrogen radials and ions. This invention makes it possible to use oxygen as a precursor in the deposition of the metal gates. The barrier film also allows the use of hydrogen plasma in the form of either direct or remote plasma in the deposition of the gate electrode. Furthermore, the barrier film prevents the electrode material from reacting with the gate dielectric material. The barrier layer is ultra thin and, at the same time, it forms a uniform cover over the entire surface of the gate dielectric.
REFERENCES:
patent: 5625217 (1997-04-01), Chau et al.
patent: 5783478 (1998-07-01), Chau et al.
patent: 6066533 (2000-05-01), Yu
patent: 6166417 (2000-12-01), Bai et al.
patent: 6225168 (2001-05-01), Gardner et al.
patent: 6265258 (2001-07-01), Liang et al.
patent: 6291282 (2001-09-01), Wilk et al.
patent: 6368954 (2002-04-01), Lopatin et al.
patent: 6373111 (2002-04-01), Zheng et al.
patent: 6383879 (2002-05-01), Kizilyalli et al.
patent: 6407435 (2002-06-01), Ma et al.
patent: 6458695 (2002-10-01), Lin et al.
patent: 6482740 (2002-11-01), Soininen et al.
patent: 6506676 (2003-01-01), Park et al.
patent: 6511876 (2003-01-01), Buchanan et al.
patent: 6518106 (2003-02-01), Ngai et al.
patent: 6537901 (2003-03-01), Cha et al.
patent: 6579767 (2003-06-01), Park et al.
patent: 6596576 (2003-07-01), Fu et al.
patent: 6627503 (2003-09-01), Ma et al.
patent: 6696332 (2004-02-01), Visokay et al.
patent: 6700771 (2004-03-01), Bhattacharyya
patent: 6713846 (2004-03-01), Senzaki
patent: 6714435 (2004-03-01), Dimmler et al.
patent: 6717226 (2004-04-01), Hegde et al.
patent: 6723581 (2004-04-01), Chabal et al.
patent: 6730163 (2004-05-01), Vaartstra
patent: 6730588 (2004-05-01), Schinella
patent: 20010041250 (2001-11-01), Werkhoven et al.
patent: 20020008257 (2002-01-01), Barnak et al.
patent: 20020096724 (2002-07-01), Liang et al.
patent: 20030165615 (2003-09-01), Aaltonen et al.
patent: 0854 505 (1998-07-01), None
patent: WO 9414198 (1994-06-01), None
patent: WO 0129893 (2001-04-01), None
patent: WO 0166832 (2001-09-01), None
patent: WO 0243115 (2002-05-01), None
patent: WO 0250922 (2002-06-01), None
Suntola, T. “Atomic Layer Epitaxy”, Handbook of Crystal Growth, vol. 3, Chapter 14, NH 1994, pp. 605-663.
Chatterjee et al., “CMOS Metal Replacement Gate Transistors using Tantalum Pentoxide Gate Insulator,” IEEE, IEDM, 0-7803-4774-9/98, pp. 777-780 (1998).
Chen et al., “0.18 μm Metal Gate Fully-Depleted SOI MOSFETs for Advanced CMOS Applications,” Symposium on VLSI Technology Digest of Technical Papers, pp. 25-26 (1999).
Ducroquet et al., “Full CMP Integration of CVD TiN Damascene Sub-0.1 μMetal Gate Devices For ULSI Applications,” IEEE Transactions on Eectron Devices, vol. 48, No. 8, pp. 1816-1821 (2001).
Ferguson et al., “Titanium Nitride Metal Gate Electrode: Effect of Nitrogen Incorporation,” Advanced Metallization Conference 2001 (AMC 2001), pp. 115-119.
Hobbs et al., “Sub-Quarter Micron CMOS Process for TiN-Gate MOSFETs with TiO2 Gate Dielectric formed by Titanium Oxidation,” Advanced Products Research and Development Lab, Symposium on VLSi Technology Digest of Technical Papers, pp. 133-134 (1999).
Maiti et al., “PVD TiN Metal Gate MOSFETs on Bulk Silicon and Fully Depleted Silicon-On-Insulator (FDSOI) Substrates for Deep Sub-Quarter Micron CMOS Technology,” IEEE, IEDM, 0-7803-4774-9/98, pp. 781-784 (1998).
Park et al., “Robust Ternary Metal Gate Electrodes for Dual Gate CMOS Devices,” IEEE, IEDM, 0-7803-7050-3/02, pp. 671-674 (2001).
Polishchuk, “Dual Work Function Metal Gate CMOS Technology Using Metal Interdiffusion,” IEEE Electron Device Letter, vol. 22, No. 9, pp. 444-446 (2001).
Wakabayashi et al., “A Novel W/TiNx Metal Gate CMOS Technology using Nitrogen-Concentration-Controlling TiNx Film,” IEEE, IEDM, 0-7803-5410-9/99, pp. 253-256 (1999).
Yagishita et al., “High Performance Damascene Metal Gate MOSFET's for 0.1 μm Regime,” IEEE Transactions on Electron Devices, vol. 47, No. 5, pp. 1028-1034 (2000).
Yagishita et al., “Reduction of Threshold Voltage Deviation in Damascene Metal Gate MOSFET's,” IEEE, IEDM, 0-7083-5410-9/99, pp. 257-260 (1999).
Yeo et al., “Dual-Metal Gate CMOS Technology with Ultrathin Silicon Nitride Gate Dielectric,” IEEE Electronic Device Letters, vol. 22, No. 5, pp. 227-229 (2001).
Zhong et al., “Electrical Properties of RuO2Gate Electrodes for Dual Metal Gate Si-CMOS,” IEEE Electron Device Letters, vol. 21, No. 12, Dec. 2000, pp. 593-595.
Haukka Suvi
Huotari Hannu
ASM International NV
Knobbe Martens & Olson Bear LLP.
Lindsay Jr. Walter L.
Niebling John F.
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