Ferroelectric memory device and control method thereof

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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C365S230060, C365S189050

Reexamination Certificate

active

06967860

ABSTRACT:
A ferroelectric random access memory device including a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

REFERENCES:
patent: 6385078 (2002-05-01), Jeon
patent: 6847537 (2005-01-01), Jeon et al.

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