Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2005-10-25
2005-10-25
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030
Reexamination Certificate
active
06958944
ABSTRACT:
A method and circuits are disclosed for refreshing a memory module. After receiving a refresh address identifying a word line to be refreshed, the refresh address is located in one of a predetermined number of memory blocks of the memory module that is monitored. It is further determined whether the word line has been accessed while the memory block is being monitored. If it is determined that the word line has not been accessed, the word line is refreshed. If it is determined that the word line has been accessed, the refreshing operation is skipped for that word line.
REFERENCES:
patent: 5522064 (1996-05-01), Aldereguia et al.
patent: 5835436 (1998-11-01), Ooishi
patent: 5914902 (1999-06-01), Lawrence et al.
patent: 6118719 (2000-09-01), Dell et al.
patent: 6233193 (2001-05-01), Holland et al.
patent: 6317657 (2001-11-01), George
patent: 6463001 (2002-10-01), Williams
patent: 6707745 (2004-03-01), Mizugaki
patent: 6711081 (2004-03-01), Jain
patent: 6779136 (2004-08-01), Richter et al.
Duane Morris LLP
Phan Trong
Taiwan Semiconductor Manufacturing Co. Ltd.
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