Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-11-22
2005-11-22
Vital, Pierre M. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S125000, C712S207000, C712S210000
Reexamination Certificate
active
06968430
ABSTRACT:
A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In one embodiment, the circuit and method are adapted to format and align the prefetched instructions into predecoded instructions, and determine mapping information relating the prefetched instructions to the predecoded instructions. In addition, the circuit and method may be adapted to store the mapping information along with corresponding predecoded instructions. By determining the mapping information prior to storage of the mapping information within the lower-level memory device, the circuit and method advantageously increases the rate at which the predecoded instructions may be fetched from the lower-level memory device.
REFERENCES:
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 6275927 (2001-08-01), Roberts
patent: 6460116 (2002-10-01), Mahalingaiah
patent: 6792524 (2004-09-01), Peterson et al.
Daffer McDaniel LLP
Vital Pierre M.
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