Static information storage and retrieval – Read/write circuit
Patent
1993-03-03
1994-08-30
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
36523003, 36523009, 365233, 36523005, G11C 1928
Patent
active
053434250
ABSTRACT:
A semiconductor memory device has a memory cell array including many memory cells, a first data I/O section for implementing random input and output of data for the memory cells based on an externally-supplied random I/O signal, a second data I/O section for implementing serial input and output of data for the memory cells, a counter for counting the number of externally-supplied basic clock signal cycles, a controller for controlling the I/O of data for the memory cells in accordance with the number of the cycles of basic clock signals. The counter is capable of inputting at least one kind of externally-supplied designation signals, generating a designation control signal for designating a specified cycle which is a count starting cycle for the basic clock signal at each designation signals, generating instructions for commencement of count for the number of cycles of the basic clock signal in the counter based on the designated control signal, and synchronously controlling designation of addresses based on the number of cycles counted by the counter and the I/O operations of the first data I/O means and the second data I/O means from the specified cycle of the designated basic clock signal.
REFERENCES:
patent: 4644502 (1987-02-01), Kawashima
patent: 5206834 (1993-04-01), Okitaka et al.
Bursky, "Integrated Cached Dram Lets Data Flow at 100 MHz", Electronic Design, vol. 40, No. 4, pp. 142, 146 (Feb. 1992).
Saito Shozo
Toda Haruki
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
Le Vu
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