Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-06-21
2005-06-21
Huynh, Andy (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S339000, C257S343000, C257S408000, C257S409000, C257S493000
Reexamination Certificate
active
06909143
ABSTRACT:
A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate202formed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layer206of p-type material and a second buried layer208formed of n-type material. Layers206and208are arranged at the boundary between the semiconductor substrate and the drift region. A first well region210of p-type material contacts the first buried layer206n-type in a first portion1of the drift region. A first source region214conductivity in a predetermined upper region of the first well region, a drain region formed of a material having second conductivity type impurities in a predetermined region of the drift region, the drain region being spaced a predetermined gap apart from the first well region, a third buried layer formed of a material having first conductivity type impurities in a second region of the drift region, the third buried layer being overlapped with a part of an upper portion of the first buried layer, a second well region formed of a material having first conductivity type impurities in the second region of the drift region, the second well region being overlapped with the third buried layer, a second source region formed of a material having second conductivity type impurities in a predetermined upper region of the second well region, a gate insulating layer formed in a first channel region inside the first well region and in a second channel region inside the second well region, a gate electrode formed on the gate insulating layer, a source electrode formed to be electrically connected to the first source region and the second source region, and a drain electrode formed to be electrically connected to the drain region.
REFERENCES:
patent: 5386136 (1995-01-01), Williams et al.
patent: 6168983 (2001-01-01), Rumennik et al.
Choi Young-Suk
Jeon Chang-Ki
Kim Jong-Jib
Fairchild Korea Semiconductor
FitzGerald Esq. Thomas R.
Huynh Andy
LandOfFree
Lateral double-diffused MOS transistor having multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lateral double-diffused MOS transistor having multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lateral double-diffused MOS transistor having multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3462749