Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-06-14
2005-06-14
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S352000, C257S369000
Reexamination Certificate
active
06906383
ABSTRACT:
There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.
REFERENCES:
patent: 4965213 (1990-10-01), Blake
patent: 5146291 (1992-09-01), Watabe et al.
patent: 5147826 (1992-09-01), Liu et al.
patent: 5165075 (1992-11-01), Hiroki et al.
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5217913 (1993-06-01), Watabe et al.
patent: 5275851 (1994-01-01), Fonash et al.
patent: 5287205 (1994-02-01), Yamazaki et al.
patent: 5289030 (1994-02-01), Yamazaki et al.
patent: 5292675 (1994-03-01), Codama
patent: 5308780 (1994-05-01), Chou et al.
patent: 5308998 (1994-05-01), Yamazaki et al.
patent: 5323042 (1994-06-01), Matsumoto
patent: 5359219 (1994-10-01), Hwang
patent: 5366915 (1994-11-01), Kodama
patent: 5413945 (1995-05-01), Chien et al.
patent: 5444282 (1995-08-01), Yamaguchi et al.
patent: 5516711 (1996-05-01), Wang
patent: 5523257 (1996-06-01), Yamazaki et al.
patent: 5532176 (1996-07-01), Katada et al.
patent: 5547883 (1996-08-01), Kim
patent: 5591650 (1997-01-01), Hsu et al.
patent: 5610089 (1997-03-01), Iwai et al.
patent: 5614432 (1997-03-01), Goto
patent: 5650338 (1997-07-01), Yamazaki et al.
patent: 5677224 (1997-10-01), Kadosh et al.
patent: 5710451 (1998-01-01), Merchant
patent: 5736750 (1998-04-01), Yamazaki et al.
patent: 5767930 (1998-06-01), Kobayashi et al.
patent: 5773347 (1998-06-01), Kimura et al.
patent: 5804472 (1998-09-01), Balasanski et al.
patent: 5827747 (1998-10-01), Wang et al.
patent: 5841170 (1998-11-01), Adan et al.
patent: 5891766 (1999-04-01), Yamazaki et al.
patent: 5913112 (1999-06-01), Yamazaki et al.
patent: RE36314 (1999-09-01), Yamazaki et al.
patent: 5962870 (1999-10-01), Yamazaki et al.
patent: 6100561 (2000-08-01), Wang et al.
patent: 6114728 (2000-09-01), Yamazaki et al.
patent: 6222238 (2001-04-01), Chang et al.
patent: 6388291 (2002-05-01), Zhang et al.
patent: 6417543 (2002-07-01), Yamazaki et al.
patent: 6433361 (2002-08-01), Zhang et al.
patent: 0 487 220 (1992-05-01), None
patent: 58-142566 (1983-08-01), None
patent: 63-313814 (1988-12-01), None
patent: 01-307266 (1989-12-01), None
patent: 2-148865 (1990-06-01), None
patent: 2-153538 (1990-06-01), None
patent: 03-024735 (1991-02-01), None
patent: 3-203322 (1991-09-01), None
patent: 03-283626 (1991-12-01), None
patent: 04-188633 (1992-07-01), None
patent: 04-320036 (1992-11-01), None
patent: 5-114724 (1993-05-01), None
patent: 05-121433 (1993-05-01), None
patent: 5-142577 (1993-06-01), None
patent: 05-241201 (1993-09-01), None
patent: 5-315355 (1993-11-01), None
patent: 7-106337 (1995-04-01), None
Wolf et al., “Silicon Processing for the VLSI Era,” vol. I, Lattice Press, 1986 pp. 292-294.
R. Kakkad et al., “Crystallized Si films by low-temperature rapid thermal annealing of amorphous silicon,”J. Appl. Phys., 65(5), Mar. 1, 1989, pp. 2069-2072.
G. Liu et al., “Polycrystalline silicon thin film transistors on Corning 7059 glass substrates using short time, low-temperature processing,”Appl. Phys. Lett.62(20), May 17, 1993, pp. 2554-2556.
G. Liu et al., “Selective area crystallization of amorphous silicon films by low-temperature rapid thermal annealing,”Appl. Phys. Lett.55(7), Aug. 14, 1989, pp. 660-662.
R. Kakkad et al., “Low Temperature Selective Crystallization of Amorphous Silicon,”Journal of Non-Crystalline Solids115, 1989, pp. 66-68.
C. Hayzelden et al., “In Situ Transmission Electron Microscopy Studies of Silicide-Mediated Crystallization of Amorphous Silicon” (3 pages).
A. V. Dvurechenskii et al., “Transport Phenomena in Amorphous Silicon Doped by Ion Implantation of 3d Metals”,Akademikian Lavrentev Prospekt13, 630090 Novosibirsk 90, USSR, pp. 635-640.
T. Hempel et al., “Needle-Like Crystallization of Ni Doped Amorphous Silicon Thin Films”,Solid State Communications, vol. 85, No. 11, pp. 921-924, 1993.
Wolf, Silicon Processing for the VLSI Era, vol. 2—Process Integration, Lattice Press, 1990, pp. 66-67, 1990.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1—Process Technology, Lattice Press, 1986, pp. 397-399, 1986.
U.S. Appl. No. 08/922,363 filed Sep. 3, 1997.
U.S. Appl. No. 09/526,487 Filed Mar. 15, 2000.
Konuma Toshimitsu
Ohnuma Hideto
Suzawa Hideomi
Takemura Yasuhiko
Uochi Hideki
Abraham Fetsum
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Semiconductor device and method of manufacture thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacture thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacture thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3462151