Synchronous content addressable memory

Details Synchronous content addressable memory Synchronous content addressable memory

2005-11-01

2005-11-01

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S049130

Reexamination Certificate

active

06961810

ABSTRACT:
A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

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