Pseudostatic memory circuit

Details Pseudostatic memory circuit Pseudostatic memory circuit

2005-06-21

2005-06-21

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S236000, C365S189011

Reexamination Certificate

active

06909657

ABSTRACT:
A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

REFERENCES:
patent: 6392958 (2002-05-01), Lee
patent: 6542425 (2003-04-01), Nam
patent: 2002/0027821 (2002-03-01), Mizugaki
Sawada, K. et al.: “A 30- μA Data-Retention Pseudostatic RAM with Virtually Static RAM Mode”, IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 12-19.

Affiliated with

Also associated with

Rating

Pseudostatic memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pseudostatic memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pseudostatic memory circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3459807