System latency levelization for read data

Details System latency levelization for read data System latency levelization for read data

2005-02-01

2005-02-01

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C711S105000, C711S167000, C711S169000, C711S170000, C365S194000

Reexamination Certificate

active

06851016

ABSTRACT:
In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

REFERENCES:
patent: 5778446 (1998-07-01), Kim
patent: 5890195 (1999-03-01), Rao
patent: 5917760 (1999-06-01), Millar
patent: 5987244 (1999-11-01), Kau et al.
patent: 6125421 (2000-09-01), Roy
patent: 6154821 (2000-11-01), Barth et al.
patent: 6182112 (2001-01-01), Malek et al.
patent: 6442644 (2002-08-01), Gustavson et al.
patent: 6445624 (2002-09-01), Janzen et al.
patent: 0 852 380 (1998-07-01), None
patent: 0 852 380 (1999-09-01), None
patent: WO 9919876 (1999-04-01), None

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