Semiconductor device having memory cell portion and...

Details Semiconductor device having memory cell portion and... Semiconductor device having memory cell portion and...

Filed on

2005-03-08

Date issued

2005-03-08

Examiner

Nelms, David (Department: 2818)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Field effect device

SubSubClass

Having insulated electrode

Other Related Categories

C257S303000, C257S306000, C257S310000, C257S311000

Type

Reexamination Certificate

Status

active

Patent number

06864546

Description

ABSTRACT:
A semiconductor device having a memory cell portion and a peripheral circuit portion is provided which achieves suppression of reduction of punch-through margin of transistors in the peripheral circuit portion and offers ensured short margin and enhanced current driving capability. After a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to improve burying characteristics after formation of an interlayer insulating film, and also after a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to enhance refresh characteristics after formation of contact plugs in the memory cell portion, a silicon oxide film and insulating film formed on a semiconductor substrate in the peripheral circuit portion are removed by anisotropic dry-etching, leaving the insulating film as sidewall insulating films on sides of sidewall nitride films. Then an impurity ion implantation process is performed using gate interconnections as implant masks to form source/drain regions in the peripheral circuit portion.

REFERENCES:
patent: 6433381 (2002-08-01), Mizutani et al.
patent: 6744091 (2004-06-01), Ema et al.
patent: 3-212974 (1991-09-01), None
patent: 6-216333 (1994-08-01), None

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