Design verification system for avoiding false failures and...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

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06931611

ABSTRACT:
Embodiments of the present invention provide for a method and system for verifying that an implementation design is functionally equivalent to a predetermined functionality of a reference design where the reference and implementation designs may correspond to a portion of a larger integrated circuit design. The use of Symbolic Trajectory Evaluation (STE) to compare the designs may result in false failures. Therefore, one aspect of the present invention provides for comparing an expected result from the reference design to an actual result of the implementation design in order to determine a set of failure conditions. Constraints are then selectively applied to the set of failure conditions in an attempt to remove them. Another aspect of the present invention allows for the selective use of symbols rather than “X”s (unknowns) in order to avoid false failures due to certain inputs of the implementation design not being properly stimulated.

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A. Hu, Formal hardware Verification with BDDs: An Introduction, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 677-682, Aug. 1997.
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Narayanan Krishnamurthy et al., “Design and Development Paradigm for Industrial Formal Verification CAD Tools”, IEEE Design & Test of Computers, Jul.-Aug. 2001, pp. 26-35.
J.R. Burch et al., “Representing Circuits More Efficiently in Symbolic Model Checking”, 1991 28thACM/IEEE Design Automation Conference, Paper 24.3, pp. 403-407.

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