Self-aligned gate formation using polysilicon polish with...

Details Self-aligned gate formation using polysilicon polish with... Self-aligned gate formation using polysilicon polish with...

2005-08-02

2005-08-02

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S594000, C438S257000, C257S315000, C257S316000

Reexamination Certificate

active

06924220

ABSTRACT:
A method of protecting a peripheral region, by forming a protective mask over the peripheral area, during polysilicon polishing while forming self-aligned polysilicon gates in flash memory circuits. In one aspect, the protective mask is formed over a substantial area of the Peripheral region. In another aspect, the protective mask is formed over a substantial area of an active part of the peripheral region.

REFERENCES:
patent: 6271561 (2001-08-01), Doan

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