Semiconductor memory array of floating gate memory cells...

Details Semiconductor memory array of floating gate memory cells... Semiconductor memory array of floating gate memory cells...

2005-10-04

2005-10-04

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S317000, C257S321000

Reexamination Certificate

active

06952033

ABSTRACT:
A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends vertically along a sidewall of the trench and a second portion that extends horizontally along the substrate surface. An electrically conductive floating gate is formed over and insulated from a portion of the channel region. A raised source line of conductive material is disposed over the source region, and laterally adjacent to and insulated from the floating gate. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.

REFERENCES:
patent: 4757360 (1988-07-01), Faraone
patent: 4794565 (1988-12-01), Wu et al.
patent: 4882707 (1989-11-01), Mizutani
patent: 4905062 (1990-02-01), Esquivel et al.
patent: 4931847 (1990-06-01), Corda
patent: 4947221 (1990-08-01), Stewart et al.
patent: 5021848 (1991-06-01), Chiu
patent: 5029130 (1991-07-01), Yeh
patent: 5041886 (1991-08-01), Lee
patent: 5049515 (1991-09-01), Tzeng
patent: 5101250 (1992-03-01), Arima et al.
patent: 5268319 (1993-12-01), Harari
patent: 5338953 (1994-08-01), Wake
patent: 5381028 (1995-01-01), Iwasa
patent: 5429965 (1995-07-01), Shimoji
patent: 5495441 (1996-02-01), Hong
patent: 5544103 (1996-08-01), Lambertson
patent: 5572054 (1996-11-01), Wang et al.
patent: 5780341 (1998-07-01), Ogura
patent: 5780892 (1998-07-01), Chen
patent: 5789293 (1998-08-01), Cho et al.
patent: 5796139 (1998-08-01), Fukase
patent: 5808328 (1998-09-01), Nishizawa
patent: 5811853 (1998-09-01), Wang
patent: 5814853 (1998-09-01), Chen
patent: 5943572 (1999-08-01), Krautschneider
patent: 5998261 (1999-12-01), Hofmann et al.
patent: 6091104 (2000-07-01), Chen
patent: 6103573 (2000-08-01), Harari et al.
patent: 6140182 (2000-10-01), Chen
patent: 6180458 (2001-01-01), Krautschneider et al.
patent: 6222227 (2001-04-01), Chen
patent: 6262917 (2001-07-01), Lee
patent: 6316298 (2001-11-01), Lee
patent: 6316315 (2001-11-01), Hofmann et al.
patent: 6521944 (2003-02-01), Mirgorodski
patent: 6538275 (2003-03-01), Sugiyama et al.
patent: 6541815 (2003-04-01), Mandelman et al.
patent: 6756633 (2004-06-01), Wang et al.
patent: 2003/0073275 (2003-04-01), Kianian
patent: 0 389 721 (1990-10-01), None
U.S. Appl. No. 09/401,622, Sep. 22, 1999, Johnson.
Hayashi, et al., “A Self-Aligned Split-Gate Flash EEPROM Cell With 3-D Pillar Structure,” 1999 Symposium on VLSI Technology Digest of Technology Papers, pp. 87-88, Center for Integrated Systems, Stanford University, Stanford, CA 94305, USA.
SZE, Simon, “Physics of Semiconductor Devices”, 2nd Edition, Wiley-Interscience, Basic Device Characteristics, pp. 438-439.
Brown, William D., et al..; “Nonvolatile Semiconductor Memory Technology, A Comprehensive Guide to Understanding And Using NVSM Devices”, IEEE Press, pp. 33-34.
U.S. Appl. No. 10/653,015, Aug. 2003, Chen et al.
U.S. Appl. No. 10/776,397, Feb. 2004, Kianian et al.
U.S. Appl. No. 10/818,590, Apr. 2004, Kianian et al.
U.S. Appl. No. 10/776,483, Feb. 2004, Kianian et al.

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