Method of shallow trench isolation formation and planarization

Details Method of shallow trench isolation formation and planarization Method of shallow trench isolation formation and planarization

2005-09-27

2005-09-27

Deo, Duy-Vu N. (Department: 1765)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S425000, C438S433000, C438S434000, C438S714000, C438S723000, C438S756000

Reexamination Certificate

active

06949446

ABSTRACT:
Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.

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