Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-08-09
2005-08-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S253000, C438S396000, C438S637000, C438S778000
Reexamination Certificate
active
06927170
ABSTRACT:
Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.
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Fourson George
Garcia Joannie Adelle
TraskBritt
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