Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-10-25
2005-10-25
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C712S010000, C712S215000, C717S149000
Reexamination Certificate
active
06959372
ABSTRACT:
A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.
REFERENCES:
patent: 3537074 (1970-10-01), Sankin et al.
patent: 4351025 (1982-09-01), Hall, Jr.
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 5121498 (1992-06-01), Gilbert et al.
patent: 5303369 (1994-04-01), Borcherding et al.
patent: 5586258 (1996-12-01), Conterno et al.
patent: 5734921 (1998-03-01), Dapp et al.
patent: 5752264 (1998-05-01), Blake et al.
patent: 5941973 (1999-08-01), Kondo et al.
patent: 6052752 (2000-04-01), Kwon
patent: 6055599 (2000-04-01), Han et al.
patent: 6205522 (2001-03-01), Hudson et al.
patent: 6351781 (2002-02-01), Gracias et al.
patent: 6493776 (2002-12-01), Courtright et al.
patent: 2004/0103263 (2004-05-01), Colavin et al.
patent: 2005/0033941 (2005-02-01), Joyce et al.
Dyck Allan R.
Hobson Richard F.
Ressl Bill
Cogent Chipware Inc.
Moazzami Nasser
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