Leak immune semiconductor memory

Static information storage and retrieval – Read/write circuit – Including signal comparison

Reexamination Certificate

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C365S154000, C365S156000

Reexamination Certificate

active

06856555

ABSTRACT:
A semiconductor memory has word lines, bit lines, memory cells configured to store signals by transition states of transistors and configured to provide the bit lines with the signals addressed by the word lines, a leak detecting line, leak generators configured to provide the leak detecting line with a leakage current and a signal compensator configured to detect a voltage state of the leak detecting line and to change the signals transmitted by the bit lines.

REFERENCES:
patent: 4879690 (1989-11-01), Anami et al.
patent: 5805508 (1998-09-01), Tobita
patent: 5986940 (1999-11-01), Atsumi et al.
patent: 6522594 (2003-02-01), Scheuerlein
Ken'ichi Agawa, et al., “A Bitline Leakage Compensation Scheme for Low-Voltage SRAMs”, IEEE Jornal of Solid-State Circuits, vol. 36, No. 5, May 2001, pp. 726-734.

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