Dual-ported read SRAM cell with improved soft error immunity

Details Dual-ported read SRAM cell with improved soft error immunity Dual-ported read SRAM cell with improved soft error immunity

2005-03-29

2005-03-29

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S206000, C365S154000, C365S189050

Reexamination Certificate

active

06873565

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for improving the soft error rate in a dual-port read SRAM cell. A write-only transfer device is connected to a cross-coupled latch, a first wordline, and a first bitline. A first read-only transfer device is connected to a second bitline, a second wordline, and a first pull-down device. A second read-only transfer device is connected to the first bitline, the first wordline, and a second pull-down device. A clear memory transfer device is connected to the cross-coupled latch, a third bitline, and a third pull-down device. This configuration allows a reduction in the size of a dual-port SRAM cell with little or no reduction in the read access time of the cell. The reduction in size also reduces SER by reducing the cross-sectional, p
junction area exposed to radiation.

REFERENCES:
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patent: 6215694 (2001-04-01), Li et al.
patent: 6504788 (2003-01-01), Nii et al.
patent: 6510076 (2003-01-01), Lapadat et al.
patent: 6639866 (2003-10-01), Slamowitz et al.
patent: 6807081 (2004-10-01), Nii

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