Stacked gate region of a memory cell in a memory device

Details Stacked gate region of a memory cell in a memory device Stacked gate region of a memory cell in a memory device

2005-09-27

2005-09-27

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000

Reexamination Certificate

active

06949792

ABSTRACT:
Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

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