Method for making a semiconductor device with a high-k gate...

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate

Reexamination Certificate

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C438S591000, C438S785000, C438S216000, C438S287000

Reexamination Certificate

active

06887800

ABSTRACT:
A method for making a semiconductor device is described. That method comprises modifying a first surface, and forming a high-k gate dielectric layer on an unmodified second surface.

REFERENCES:
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6255698 (2001-07-01), Gardner et al.
patent: 6365450 (2002-04-01), Kim
patent: 6410376 (2002-06-01), Ng et al.
patent: 6420279 (2002-07-01), Ono et al.
patent: 6475874 (2002-11-01), Xiang et al.
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6544906 (2003-04-01), Rotondaro et al.
patent: 6586288 (2003-07-01), Kim et al.
patent: 6617209 (2003-09-01), Chau et al.
patent: 6617210 (2003-09-01), Chau et al.
patent: 6620713 (2003-09-01), Arghavani et al.
patent: 6642131 (2003-11-01), Harada
patent: 6667246 (2003-12-01), Mitsuhashi et al.
patent: 6689675 (2004-02-01), Parker et al.
patent: 6696327 (2004-02-01), Brask et al.
patent: 6696345 (2004-02-01), Chau et al.
patent: 20020058374 (2002-05-01), Kim et al.
patent: 20020197790 (2002-12-01), Kizilyalli et al.
patent: 20030032303 (2003-02-01), Yu et al.
patent: 20030045080 (2003-03-01), Visokay et al.
patent: 0 899 784 (1999-03-01), None
patent: 2 358 737 (2001-04-01), None
Polishchuk et al., “Dual Workfunction CMOS Gate Technology Based on Metal Interdiffusion”, www.eesc.berkeley.edu, 1 page.
Doug Barlage et al., “High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics”, 2001 IEEE, 4 pages.
Lu et al., “Dual-Metal Gate Technology for Deep-Submicron CMOS Devices”, dated Apr. 29, 2003, 1 page.
Schwantes et al., “Performance Improvement of Metal Gate CMOS Technologies with Gigabit Feature Sizes”, Technical University of Hanburg-Harburg, 5 pages.
U.S. Appl. No. 10/327,293, filed Dec. 20, 2002, Doczy et al., “Integrating N-type and P-type Metal Gate Transistors”.
U.S. Appl. No. 10/704,497, filed Nov. 6, 2003, Brask et al., “A Method for Making a Semiconductor Device Having a Metal Gate Electrode”.
U.S. Appl. No. 10/704,498, filed Nov. 6, 2003, Brask et al., “A Method for Etching a Thin Metal Layer”.
U.S. Appl. No. 10/742,678, filed Dec. 19, 2003, Brask et al., “A Method for Making a Semiconductor Device with a Metal Gate Electrode that is Formed on an Annealed High-K Gate Dielectric Layer”.
U.S. Appl. No. 10/739,173, filed Dec. 18, 2003, Brask et al., “A Method for Making a Semiconductor Device that includes a Metal Gate Electrode”.
U.S. Appl. No. 10/748,559, filed Dec. 29, 2003, Brask et al., “A CMOS Device With Metal and Silicide Gate Electrodes and a Method for Making It”.
U.S. Appl. No. 10/748,545, filed Dec. 29, 2003, Doczy et al., “A Method for Making a Semiconductor Device that Includes a Metal Gate Electrode”.
U.S. Appl. No. 10/805,880, filed Mar. 22, 2004, Shah et al., “A Method for Making a Semiconductor Device with a Metal Gate Electrode”.
U.S. Appl. No. 10/809,853, filed Mar. 24, 2004, Shah et al., “A Replacement Gte Process for Making a Semiconductor Device that Includes a Metal Gate Electrode”.
U.S. Appl. No. 10/898,958, filed Apr. 20, 2004, Brask et al., “A Method for Making a Semiconductor Device Having a High-K Gate Dielectric Layer and a Metal Gate Electrode”.
U.S. Appl. No. unknown, filed May 4, 2004, Metz et al., “A Method for Making a Semiconductor Device Having a High-K Gate Dielectric Layer and a Metal Gate Electrode”.
U.S. Appl. No. unknown, filed May 26, 2004, Brask et al., “A Method for Making a Semiconductor Device with a High-K Gate Dielecteic and a Conductor that Facilitates Current Flow Across a P/N Junction”.

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