Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-08-02
2005-08-02
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S072000, C257S335000, C257S336000, C257S353000, C257S344000, C257S408000, C257S346000, C257S022000, C257S027000, C257S066000, C257S330000, C257S332000
Reexamination Certificate
active
06924528
ABSTRACT:
In a bottom gate type semiconductor device made of a semiconductor layer with crystal structure, source/drain regions are constructed by a lamination layer structure including a first conductive layer (n+layer), a second conductive layer (n−layer) having resistance higher than the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i layer). At this time, the n−layer acts as LDD region, and the i layer acts as an offset region is a film thickness direction.
REFERENCES:
patent: 5457058 (1995-10-01), Yonehara
patent: 5595944 (1997-01-01), Zhang et al.
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5677211 (1997-10-01), Kaneko
patent: 5825050 (1998-10-01), Hirakawa
patent: 5828082 (1998-10-01), Wu
patent: 5904509 (1999-05-01), Zhang et al.
patent: 5917199 (1999-06-01), Byun et al.
patent: 5936278 (1999-08-01), Hu et al.
patent: 5952708 (1999-09-01), Yamazaki
patent: 5990542 (1999-11-01), Yamazaki
patent: 6013930 (2000-01-01), Yamazaki et al.
patent: 6169293 (2001-01-01), Yamazaki
patent: 6197624 (2001-03-01), Yamazaki
patent: 6204535 (2001-03-01), Yamazaki et al.
patent: 6218219 (2001-04-01), Yamazaki et al.
patent: 6239470 (2001-05-01), Yamazaki
patent: 6407431 (2002-06-01), Yamazaki et al.
patent: 6429059 (2002-08-01), Yamazaki et al.
patent: 6441468 (2002-08-01), Yamazaki
patent: 6445059 (2002-09-01), Yamazaki
patent: 6563136 (2003-05-01), Kunii
patent: 6787887 (2004-09-01), Yamazaki
patent: 6800875 (2004-10-01), Yamazaki
patent: 7-130652 (1995-05-01), None
patent: 8-15686 (1996-01-01), None
patent: 8-306639 (1996-11-01), None
H. Hayashi et al., “Fabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate by Linear-Beam Excimer Laser Crystallization and Ion Doping Method,” IEDM95, pp. 829-832, 1995.
Kim et al., “4.4: Planarized Black Matrix on TFT Structure for TFT-LCD Monitors,” 1997, pp. 19-22, SID 97 Digest.
U.S. Appl. No. 10/141,821, including specification, drawing, and filing receipt, “Semiconductor Device and Fabrication Method Thereof,” Shunpei Yamazaki, et al., May 10, 2002.
Fukunaga Takeshi
Koyama Jun
Yamazaki Shunpei
Nguyen Joseph
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
Wilson Allan R.
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