Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2005-05-31
2005-05-31
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S723000, C257S778000
Reexamination Certificate
active
06900538
ABSTRACT:
Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.
REFERENCES:
patent: 5055907 (1991-10-01), Jacobs
patent: 5192716 (1993-03-01), Jacobs
patent: 5527741 (1996-06-01), Cole et al.
Dr. Luu Nguyen et al, Assembly Considerations for micro SMD Wafer-Level CSPs, Chip Scale Review, May/Jun. 2000, p. 48 et seq.
James L. Young, Wafer-Level Processing: Working Smarter, Chip Scale Review, May 1997, p. 28 et seq.
Dr. Philip Garrou, Wafer-Level Packaging Has Arrived, Semiconductor International, Oct. 2000, p. 119 et seq.
Alter Martin
Rumsey Robert
Micrel Inc.
Potter Roy
Tortolano J. Vincent
Valet Eugene H.
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