Methods and arrangements to enhance an upbound path

Details Methods and arrangements to enhance an upbound path Methods and arrangements to enhance an upbound path

2005-01-11

2005-01-11

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06842828

ABSTRACT:
A cache coherency arrangement to enhance an upbound path for input-output interfaces is disclosed. Several embodiments may enhance upbound write bandwidth and buffer utilization. Some embodiments may comprise requesting content of a memory granule and merging the content with data associated with a write request for the memory granule prior to satisfaction of an ordering rule associated with the write request. Many embodiments may comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation and/or deadlock of transactions or of an input-output interface for transactions. Such embodiments may also comprise invalidating merged content of the memory granule. Further embodiments may comprise reverting the merged content to the data associated with the write request.

REFERENCES:
patent: 6405276 (2002-06-01), Chen et al.
patent: 6760793 (2004-07-01), Kelley et al.

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