Method of fabricating a ferroelectric stacked memory cell

Details Method of fabricating a ferroelectric stacked memory cell Method of fabricating a ferroelectric stacked memory cell

2005-03-29

2005-03-29

Tsai, H. Jey (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000

Reexamination Certificate

active

06872996

ABSTRACT:
The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

REFERENCES:
patent: 5350705 (1994-09-01), Brassington et al.
patent: 5418388 (1995-05-01), Okudaira et al.
patent: 5519237 (1996-05-01), Itoh et al.
patent: 5796133 (1998-08-01), Kwon et al.
patent: 5796136 (1998-08-01), Shinkawata
patent: 5955758 (1999-09-01), Sandhu et al.
patent: 6028361 (2000-02-01), Ooishi
patent: 6063656 (2000-05-01), Clampitt
Amanuma, K. et al., “Capacitor-on-Metal/Via-stacked-Plug (CMVP) Memory Cell for 0.25um CMOS Embedded Fe RAM”,IEEE, 1998, p. 363-366.
Jones, Robert E. Jr., “Integration of Ferroelectric Nonvolatile Memories,”Solid State Technology, Oct. 1997, pp. 201-210.
Takashima, D. et al., “A Sub-40ns Random-Access Chain FRAM Architecture with a 7ns Cell-Plate-Line Drive,”IEEE International Solid-State Circuits Conference, 1999, pp. 102-103.
Yamazaki, T., et al., “Advanced 0.5um FRAM Device Technology with Full Compatibility of Half-Micron CMOS Logic device”,Advanced Process Integration Department, Fujitsu Limited. (4 pages).

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