Synchronous clocked full-rail differential logic with...

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S095000, C326S113000

Reexamination Certificate

active

06876230

ABSTRACT:
In a synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. Consequently, the synchronous clocked full-rail differential logic circuits with single-rail logic and shut-off of the invention are smaller, less complex and are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient and is more resistant to noise than prior art full-rail differential logic circuits.

REFERENCES:
patent: 4247791 (1981-01-01), Rovell
patent: 5859548 (1999-01-01), Kong
patent: 6211704 (2001-04-01), Kong
Choe et al., “Dynamic Half Rail Differential Logic for Low Power”, IEEE 1997, pp. 1936 to 1939.
Jung et al., “Modular Charge Recycling pass Transistor Logic (MCRPL)”, Electronics Letters, Mar. 2, 2000 vol. 36 No. 5, Mar. 2, 2000, pp. 404 to 405.
Kong et al., “Charge Recycling Differential Logic for Low-Power Application”, ISSC96 secession 18, IEEE 0-780331962/98, 1998, pp. 302 to 448.
Choe et al., “Half Rail Differential Logic”, ISSCC97/Secession 25/Processors and Logic/Paper SP 25.6 IEEE 0-7803-3721-2/97, 1997, pp. 420 to 421, 337 and 489.
Won et al., “Modified Half Rail Differential Logic for Reduced Internal Logic Swing”, IEEE 0-7803-4455-3/98, 1998, pp. II-157 to II-160.
Kong et al., “Charge Recycling Differential Logic (CRDL) for Low-Power Application”, IEEE Journal of Solid-State Circuits, vol. 31, No. 9, Sep. 1996, pp. 1267-to 1276.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Synchronous clocked full-rail differential logic with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous clocked full-rail differential logic with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous clocked full-rail differential logic with... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3431428

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.