Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-07-05
2005-07-05
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06915467
ABSTRACT:
A system and method is disclosed for simultaneously testing columns and column redundancies of a semiconductor memory by temporarily adding an additional parallel signal bit to an input/output data bus associated therewith, the additional parallel signal bit providing greater bandwidth during test mode operation. The input/output data bus has n parallel signal bits which normally carry column data, but the additional parallel signal bit does not normally carry either column data or column redundancy data. The additional parallel signal bit may normally carry a clock signal such as an echo clock associated with the data placed on the data bus.
REFERENCES:
patent: 4449207 (1984-05-01), Kung et al.
patent: 5257229 (1993-10-01), McClure et al.
patent: 5299161 (1994-03-01), Choi et al.
patent: 5355340 (1994-10-01), Coker et al.
patent: 5502676 (1996-03-01), Pelley, III et al.
patent: 5530674 (1996-06-01), McClure et al.
patent: 5608678 (1997-03-01), Lysinger
patent: 5673227 (1997-09-01), Engles et al.
patent: 5677881 (1997-10-01), Seo et al.
patent: 5708612 (1998-01-01), Abe
patent: 5732029 (1998-03-01), Lee et al.
patent: 5809225 (1998-09-01), Ohsawa et al.
patent: 5870341 (1999-02-01), Lin et al.
patent: 6037799 (2000-03-01), McClure
patent: 6111800 (2000-08-01), Allan et al.
patent: 6122194 (2000-09-01), Chung et al.
patent: 6144593 (2000-11-01), Cowles et al.
patent: 6154389 (2000-11-01), Chung et al.
patent: 6240024 (2001-05-01), Taufique et al.
patent: 6269035 (2001-07-01), Cowles et al.
patent: 6278637 (2001-08-01), Kawaguchi
patent: 6490210 (2002-12-01), Takase et al.
patent: 10050099 (1997-09-01), None
patent: 10172294 (1998-06-01), None
“A Redundancy Test-Time Teduction Technique in 1-Mbit DRAM with a Multibit Test Mode” by Nishimura et al. IEEE Journal o Solid-State Circuits, Feb. 1989 vol.: 24, Issue: 1 p. 43-49 Inspec Accession No.: 3375644.
IBM Technical Disclosure Bulletin, vol. 34, No. 7B, Dec. 1991, Column Redundancy for Fast Memory Arrays.
IBM Technical Disclosure Bulletin, vol. 31, No. 10, Mar. 1989, Multiplexed Column Redundancy Method for Complementary Metal Oxide Silicon Memory
IEEE Xplore, A 3.3V 12 ns 16 Mb CMOS SRAM, 39th ISSCC, 1992 IEEE International, pp., 216-217, 288, Feb. 19-21, 1992,H. Goto et al., NEC Corp.
IEEE Xplore, An Approach to Testing 200 ps Echo Clock to Output Timing on the Double Data Rate Synchronous Memory, Test Conference 2000, Proceedings, International, pp. 610-618, 10/3-May 2000, Van Dinh, D.; Rabitoy, V.
Britt Cynthia
De'cady Albert
Schnurmann H. Daniel
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