Semiconductor device and method of manufacturing the same

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S637000, C438S253000, C438S256000, C438S622000

Reexamination Certificate

active

06916738

ABSTRACT:
Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

REFERENCES:
patent: 5879986 (1999-03-01), Sung
patent: 6458692 (2002-10-01), Kim
patent: 2004/0188806 (2004-09-01), Chung et al.
patent: 2001-217405 (2001-10-01), None
English Language of Abstract from Japanese Patent Publication No. 2001-217405, published Oct. 8, 2001.

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