Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-09-20
2005-09-20
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S106000, C711S005000
Reexamination Certificate
active
06948027
ABSTRACT:
A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
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Glaskowsky, Peter N., “MoSys Explains 1T-SRAM Technology,” MicroDesign Resources, MicroProcessor Report, Sep. 13, 1999, p. 23.
Dennison Charles H.
Keeth Brent
Ryan Kevin J.
Shirley Brian M.
Bragdon Reginald G.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
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