Patterning method for fabricating integrated circuit

Details Patterning method for fabricating integrated circuit Patterning method for fabricating integrated circuit

2005-09-20

2005-09-20

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S707000, C438S708000, C438S709000, C438S717000, C438S718000, C438S720000

Reexamination Certificate

active

06946400

ABSTRACT:
A patterning method for fabricating integrated circuits. The method includes forming a material layer over a substrate and then forming a photoresist layer over the material layer. The photoresist layer has a thickness small enough to relax the limitations when the photoresist layer is patterned in a photolithographic process. A shroud liner is formed over the photoresist layer such that height of the shroud liner is significantly greater than width of the shroud liner. Thereafter, the shroud liner undergoes a processing treatment to remove the sections attached to the sidewalls of the photoresist layer. Using the remaining shroud liner as an etching mask, an etching operation is carried out to pattern the material layer.

REFERENCES:
patent: 5895740 (1999-04-01), Chien et al.
patent: 6416933 (2002-07-01), Singh et al.
patent: 6451705 (2002-09-01), Trapp et al.

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