Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-03-15
2005-03-15
Zarneke, David A. (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06867129
ABSTRACT:
A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited overlying the stress-balancing layer. The stack is patterned to form the capacitors. Gate transistors are formed overlying the capacitors wherein the stress-balancing layer prevents formation of stress-induced voids during the thermal processes involved in forming the gate transistors.
REFERENCES:
patent: 5503882 (1996-04-01), Dawson
patent: 5583077 (1996-12-01), Wang et al.
patent: 5883001 (1999-03-01), Jin et al.
patent: 6136688 (2000-10-01), Lin et al.
patent: 6221794 (2001-04-01), Pangrle et al.
patent: 6287962 (2001-09-01), Lin
patent: 6414376 (2002-07-01), Thakur et al.
patent: 6468855 (2002-10-01), Leung et al.
Taiwan Semiconductor Manufacturing Company
Thomas Kayden Horstemeyer & Risley
Zarneke David A.
LandOfFree
Method of improving the top plate electrode stress inducting... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of improving the top plate electrode stress inducting..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of improving the top plate electrode stress inducting... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3421443