Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2005-03-01
2005-03-01
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S023000, C712S027000, C712S213000, C712S248000, C712S206000, C711S108000, C711S214000
Reexamination Certificate
active
06862676
ABSTRACT:
A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.
REFERENCES:
patent: 5553256 (1996-09-01), Fetterman et al.
patent: 5581684 (1996-12-01), Dudzik et al.
patent: 5761476 (1998-06-01), Martell
patent: 5790857 (1998-08-01), Clifford et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5918005 (1999-06-01), Moreno et al.
patent: 5923328 (1999-07-01), Griesmer
patent: 5933139 (1999-08-01), Feigner et al.
patent: 5961634 (1999-10-01), Tran
patent: 6005824 (1999-12-01), Crafts
patent: 6044031 (2000-03-01), Iadanza et al.
patent: 6268314 (2001-07-01), Hughes et al.
patent: 6360314 (2002-03-01), Webb, Jr. et al.
patent: 6622237 (2003-09-01), Keller et al.
patent: 6629233 (2003-09-01), Kahle
patent: 9320505 (1993-10-01), None
Knapp Micah C.
Kongetira Poonacha P.
Lamere Marc E.
Staraitis Julie M.
Kivlin B Noël
Meyertons Hood Kivlin Kowert & Goetzel PC
Pan Daniel H.
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