Integrated circuit design layout compaction method

Details Integrated circuit design layout compaction method Integrated circuit design layout compaction method

2005-03-29

2005-03-29

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06874133

ABSTRACT:
A plurality of member devices is defined in a conformal outline having a pair of spaced parallel sides. Associated with each member device is a spacing constraint that sets a minimum distance the member device can be spaced from another member device and each side of the conformal outline. The spacing between member devices and/or the sides of the conformal outline are increased and/or decreased as necessary to minimize the area of the conformal outline that the member devices are received in with no violation of the spacing constraints while excluding from the conformal outline all or part of any nonmember devices defined therein.

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