Semiconductor memory test device

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S189090, C365S230060

Reexamination Certificate

active

06891766

ABSTRACT:
A semiconductor memory test device configured to reduce level variations of a core voltage and a pumping voltage by shorting an external power voltage and the pumping voltage according to input of a test signal in an operation life test or a burn-in test, and to control levels of the core voltage and a peri voltage according to a level of the external power voltage is disclosed herein. As a result, the semiconductor memory test device is configured to obtain a sufficient margin of the external power voltage and to adaptively transmit a stress voltage to 2.5 V/3.3 V DRAM.

REFERENCES:
patent: 6661218 (2003-12-01), Kim
patent: 6751134 (2004-06-01), Choi et al.

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