Time division multiplexed serial bus with increased bandwidth

Details Time division multiplexed serial bus with increased bandwidth Time division multiplexed serial bus with increased bandwidth

2005-05-24

2005-05-24

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S026000

Reexamination Certificate

active

06897681

ABSTRACT:
The output of drivers which are used to drive the input signals to a multiplexed signal line are combined in a logic OR gate or a logic AND gate prior to connection to the input of the multiplexed line. The inactive state of drivers connected through a logic OR gate is set to 0 and the inactive state of drivers connected through a logic AND gate is set to 1. Bus contention between drivers is eliminated and the bandwidth of the multiplexed serial bus is increased because of the reduced wait time between driver transitions. Power dissipation in transition is reduced and the bus can have a programmable inactive state on a bus to allow for 1, 0 or High Z to indicate the inactive state.

REFERENCES:
patent: 5440247 (1995-08-01), Kaplinsky
patent: 5847580 (1998-12-01), Bapat et al.
patent: 5973506 (1999-10-01), Trimberger
patent: 5999013 (1999-12-01), Elliott
Gerald Williams, “Digital Technology”, 1981, Science Research Associates, Inc., Second Edition, p. 96, pp136-139.

Affiliated with

Also associated with

Rating

Time division multiplexed serial bus with increased bandwidth does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Time division multiplexed serial bus with increased bandwidth, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Time division multiplexed serial bus with increased bandwidth will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3418218